Regviz

Espressif Systems /ESP32-S2 /APB_SARADC /CLKM_CONF

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CLKM_CONF

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-S2/APB_SARADC/CLKM_CONF#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKM_DIV_NUM0CLKM_DIV_B0CLKM_DIV_A0CLK_SEL

Description

Configure DIG ADC clock

Fields

CLKM_DIV_NUM

Integral DIG_ADC clock divider value
CLKM_DIV_B

Fractional clock divider numerator value
CLKM_DIV_A

Fractional clock divider denominator value
CLK_SEL

1: select APLL. 2: select APB_CLK. Other values: disable clock.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data